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electronics km62v256c, km62u256c family cmos sram revision 04 april 1996 - 1 - feature summary general description the km62v256c and km62u256c family are fabricated by samsung's advanced cmos process technology. the family can support various operating temperature ranges and has various package types for user flexibility of system design. the family also support low data retention voltage for battery back-up operation with low data retention current. product family km62v256cl-l km62u256cl-l km62v256cle-l km62u256cle-l km62v256cli-l km62u256cli-l commercial (0~70 c) extended (-25~85 c) industrial (-40~85 c) 28-sop** 28-tsop(i) r/f 28-sop** 28-tsop(i) r/f 28-sop** 28-tsop(i) r/f power dissipation 10 a 10 a 20 a 15 a 20 a 15 a operating (icc2) pkg type speed (ns) operating temp. product list process technology : 0.7m cmos organization : 32k x 8 power supply voltage km62v256c family : 3.3v 0.3v km62u256c family : 3.0v 0.3v low data retention voltage : 2v(min) three state output and ttl compatible package type : jedec standard 28-sop, 28-tsop(i)-forward/reverse 32kx8 bit low power & low vcc cmos static ram pin description a10 /cs io8 io7 io6 io5 io4 vss io3 io2 io1 a0 a1 a2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 /oe a11 a9 a8 a13 /we vcc a14 a12 a7 a6 a5 a4 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vcc /we a13 a8 a9 a11 /oe a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss a3 a4 a5 a6 a7 a12 a14 vcc /we a13 a8 a9 a11 /oe 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a2 a1 a0 io1 io2 io3 vss io4 io5 io6 io7 io8 /cs a10 28-pin sop 28-pin tsop type i - forward 28-pin tsop type i - reverse * measured with 30pf test load ** the device with 100ns sop package in 3.0~3.6v vcc range is not produced. functional block diagram 35ma 28 27 26 25 24 23 22 21 20 19 18 17 16 15 standby (isb1, max) vcc range 3.0~3.6v 2.7~3.3v 3.0~3.6v 2.7~3.3v 3.0~3.6v 2.7~3.3v 70*/100 85*/100 70*/100 85*/100 70*/100 85*/100 i/o1~8 function address inputs write enable input chip select input output enable input data input/output power ground y-decoder x-decoder control logic i/o buffer cell array a3~a8 a12~14 pin name a0~a14 /we /cs /oe i/o1~i/o8 vcc vss /cs, /we /oe a0~2, a9~11
electronics km62v256c, km62u256c family cmos sram revision 04 april 1996 - 2 - product list & ordering information function commercial temp products (0~70 c) part name function extended temp products (-25~85 c) part name function industrial temp products (-40~85 c) part name product list ordering information k m6 2 x 256 c x x x - xx x access time : 7=70ns, 8=85ns, 10=100ns operating temperature : i=industrial, e=extended, blank=commercial package type : g=sop, tg=tsop forward, rg=tsop reverse die version : c=4th generation density : 256=256kbit organization : 2= x8 sec standard sram v=3.0~3.6v, u=2.7~3.3v, blank=5v km62v256clg-7l km62v256cltg-7l km62v256cltg-10l km62v256clrg-7l km62v256clrg-10l KM62U256CLG-8L km62u256cltg-8l km62u256clrg-8l km62u256clg-10l km62u256cltg-10l km62u256clrg-10l 28-sop, 70ns, 3.3v 28-tsop f, 70ns, 3.3v 28-tsop f, 100ns, 3.3v 28-tsop r, 70ns, 3.3v 28-tsop r, 100ns, 3.3v 28-sop, 85ns, 3.0v 28-tsop f, 85ns, 3.0v 28-tsop r, 85ns, 3.0v 28-sop, 100ns, 3.0v 28-tsop f, 100ns, 3.0v 28-tsop r, 100ns, 3.0v km62v256clge-7l km62v256cltge-7l km62v256cltge-10l km62v256clrge-7l km62v256clrge-10l km62u256clge-8l km62u256cltge-8l km62u256clrge-8l km62u256clge-10l km62u256cltge-10l km62u256clrge-10l 28-sop, 70ns, 3.3v 28-tsop f, 70ns, 3.3v 28-tsop f, 100ns, 3.3v 28-tsop r, 70ns, 3.3v 28-tsop r, 100ns, 3.3v 28-sop, 85ns, 3.0v 28-tsop f, 85ns, 3.0v 28-tsop r, 85ns, 3.0v 28-sop, 100ns, 3.0v 28-tsop f, 100ns, 3.0v 28-tsop r, 100ns, 3.0v km62v256clgi-7l km62v256cltgi-7l km62v256cltgi-10l km62v256clrgi-7l km62v256clrgi-10l km62u256clgi-8l km62u256cltgi-8l km62u256clrgi-8l km62u256clgi-10l km62u256cltgi-10l km62u256clrgi-10l 28-sop, 70ns, 3.3v 28-tsop f, 70ns, 3.3v 28-tsop f, 100ns, 3.3v 28-tsop r, 70ns, 3.3v 28-tsop r, 100ns, 3.3v 28-sop, 85ns, 3.0v 28-tsop f, 85ns, 3.0v 28-tsop r, 85ns, 3.0v 28-sop, 100ns, 3.0v 28-tsop f, 100ns, 3.0v 28-tsop r, 100ns, 3.0v l-low low power, blank-low power or high power l-low power or low low power, blank-high power
electronics km62v256c, km62u256c family cmos sram revision 04 april 1996 - 3 - absolute maximum ratings * voltage on any pin relative to vss voltage on vcc supply relative to vss power dissipation storage temperature operating temperature soldering temperature and time symbol vin, vout vcc pd tstg ta tsolder -0.5 to vcc+0.5 -0.3 to 4.6 0.7 -65 to 150 0 to 70 -25 to 85 -40 to 85 260 c, 10sec (lead only) unit v v w c c c c - - - - - km62v256cl-l, km62u256cl-l km62v256cle-l, km62u256cle-l km62v256cli-l, km62u256cli-l - supply voltage ground input high voltage input low voltage recommended dc operating conditions* symbol vcc vss vih vil min 3.0 2.7 0 2.2 2.2 -0.3 -0.3*** max 3.6 3.3 0 vcc+0.3 vcc+0.3 0.4 0.4 unit v v v v v v v input capacitance input/output capacitance capacitance * (f=1mhz, ta=25 c ) symbol cin cio test condition vin=0v vio=0v min - - unit pf pf max 6 8 * stresses greater than those listed under 'absolute maximum ratings' may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. * 1) commercial product : ta=0 to 70 c, unless otherwise specified 2) extended product : ta=-25 to 85 c, unless otherwise specified 3) industrial product : ta=-40 to 85 c, unless otherwise specified ** ta=25 c *** vil(min)=-3.0v for ?a 30ns pulse * capacitance is sampled not 100% tested item item item ratings remark typ** 3.3 3.0 0 - - - - product km62v256c family km62u256c family all km62v256c family km62u256c family km62v256c family km62u256c family
electronics km62v256c, km62u256c family cmos sram revision 04 april 1996 - 4 - input leakage current output leakage current operating power supply current average operating current output low voltage output high voltage standby current(ttl) standby current (cmos) km62v256cl-l km62v256cle-l km62v256cli-l km62u256cl-l km62u256cle-l km62u256cli-l dc and operating characteristics symbol ili ilo icc icc1 icc2 vol voh isb isb1 vin=vss to vcc /cs=vih or vil or /we=vil vio=vss to vcc /cs=vil, vin=vih or vil, iio=0ma cycle time=1us 100% duty /cs ?a 0.2v, vil ?a 0.2v, vin ?? vcc-0.2v, iio=0ma min cycle, 100% duty /cs=vil, iio=0ma iol=2.1ma ioh=-1.0ma /cs=vih /cs ?? vcc-0.2v vin ?a 0.2v or vin ?? vcc-0.2v unit ua ua ma ma ma v v ma ua ua ua ua ua ua max 1 1 2.0 5 35 4) 0.4 - 0.3 10 20 20 10 15 15 typ 2) - - 1.0 2.5 20 3) - - - 1.5 1.5 1.5 1.0 1.0 1.0 min -1 -1 - - - - 2.2 - - - - - - - 1) - commercial product : ta=0 to 70 c , vcc=3.0 +/- 0.3v(62u256c family), vcc=3.3 +/- 0.3v(62v256c family) - extended product : ta=-25 to 85 c , vcc=3.0 +/- 0.3v(62u256ce family), vcc=3.3 +/- 0.3v(62v256ce family) - industrial product : ta=-40 to 85 c , vcc=3.0 +/- 0.3v(62u256ci family), vcc=3.3 +/- 0.3v(62v256ci family) 2) ta=25 c 3) 25ma for km62v256c family 4) 30ma for km62u256c family but it is not 100% tested but obtained statistically low low pwr low low pwr low low pwr low low pwr low low pwr low low pwr item test conditions 1) input pulse level input rise fall time input and output reference voltage output load(see right) test conditions ( 1. test load and test input/output reference) * 0.4 to 2.2v 5ns 1.5v c l =100pf+1ttl c l =30pf+1ttl - - - - c l * * including scope and jig capacitance * see test condition of dc and operating characteristics item value remark a.c characteristics
electronics km62v256c, km62u256c family cmos sram revision 04 april 1996 - 5 - min 70 - - - 10 5 0 0 5 70 60 0 60 50 0 0 50 0 5 max - 70 70 35 - - 30 30 - - - - - - - 25 - - - min 100 - - - 10 5 0 0 15 100 70 0 70 60 0 0 60 0 10 max - 100 100 50 - - 35 35 - - - - - - - 30 - - - read cycle time address access time chip select to output output enable to valid output chip select to low-z output output enable to low-z output chip disable to high-z output output disable to high-z output output hold from address change write cycle time chip select to end of write address set-up time address valid to end of write write pulse width write recovery time write to output high-z data to write time overlap data hold from write time end write to output low-z temperature 0~70 c -25~85 c -40~85 c 0~70 c -25~85 c -40~85 c read write trc taa tco toe tlz tolz thz tohz toh twc tcw tas taw twp twr twhz tdw tdh tow ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter list 70ns 100ns symbol units test conditions (2. temperature and vcc conditions) product family km62v256cl-l km62v256cle-l km62v256cli-l km62u256cl-l km62u256cle-l km62u256cli-l power supply(vcc) 3.3v +/- 0.3 3.3v +/- 0.3 3.3v +/- 0.3 3.0v +/- 0.3 3.0v +/- 0.3 3.0v +/- 0.3 comments commercial extended industrial commercial extended industrial parameter list for each speed bin speed bin 70*/100ns 70*/100ns 70*/100ns 85*/100ns 85*/100ns 85*/100ns * all the ac parameters are measured with 30pf test load speed bins min 85 - - - 10 5 0 0 10 85 70 0 70 60 0 0 60 0 10 max - 85 85 40 - - 35 35 - - - - - - - 25 - - - 85ns
electronics km62v256c, km62u256c family cmos sram revision 04 april 1996 - 6 - km62v256cl-l km62u256cl-l km62v256cle-l km62u256cle-l km62v256cli-l km62u256cli-l vcc 3.0/2.7v* 2.2v /cs gnd /cs ?? vcc-0.2v vdr tsdr trdr data retention mode data retention timing diagram vcc for data retention data retention current data retention set-up time recovery time data retention characteristics vdr idr tsdr trdr /cs ?? vcc-0.2v vcc=3.0v /cs ?? vcc-0.2v see data retention waveform typ** - 1 0.6 1 0.6 1 0.6 - - unit v ua ms min 2.0 - - - - - - 0 5 max 3.6 8 8 10 10 10 10 - - * 1) commercial product : ta=0 to 70 c, unless otherwise specified 2) extended product : ta=-25 to 85 c, unless otherwise specified 3) industrial product : ta=-40 to 85 c, unless otherwise specified ** ta=25 c item symbol test condition* * 3.0v for km62v256c family, 2.7v for km62u256c family functional description /we x h h l mode power down output disable read write current mode isb, isb1 icc icc icc i/o pin high-z high-z dout din /oe x h l x /cs h l l l
electronics km62v256c, km62u256c family cmos sram revision 04 april 1996 - 7 - timing diagrams timing waveform of read cycle (1) (address controlled) (/cs=/oe=vil, /we=vih) address data out t rc previous data valid data valid t aa t oh timing waveform of read cycle (/we= v ih ) notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device. t rc t aa t co t oe t olz(4) t oh t lz t hz t ohz address /cs /oe data out data valid high - z
electronics km62v256c, km62u256c family cmos sram revision 04 april 1996 - 8 - timing waveform of write cycle (/we controlled) address /we data in /cs t wc t wp(1) t whz t wr(4) t dh t as t cw(2) t ow data out t aw t dw data valid data undefined timing waveform of write cycle (/cs controlled) t wc t cw(2) t wr(4) t aw t wp(1) address /cs /we data in data out t dw data valid t as high - z high - z dh t notes (write cycle) 1. a write occurs during the overlap(twp) of a low /cs and low /we. a write begins at the latest transition among /cs going low and /we going low : a write end at the earliest transition among /cs going high and /we going high, twp is measured from the beginning of write to the end of write. 2. tcw is measured from the later of /cs going low to end of write. 3. tas is measured from the address valid to the beginning of write. 4. twr is measured from the end of write to the address change. twr applied in case a write ends as /cs, or /we going high.
electronics km62v256c, km62u256c family cmos sram revision 04 april 1996 - 9 - package dimension unit : millimeters (inches) 28 pin thin small outline package type i ( 0813.4f ) 28 pin thin small outline package type i ( 0813.4r ) 0.50 0.10 0.020 0.004 0.15 0.006 +0.10 -0.05 +0.004 -0.002 11.80 0.10 (0.465 0.004) 0~8 ?? 0.55 (0.022) #1 #14 13.40 0.10 (0.528 0.008 ) #28 #15 0.20 (0.008) +0.10 -0.05 +0.004 -0.002 8.00 0.315 8.40 0.331 max. 1.20 0.047 max. 0.00 0.000 min. 0.43 0.017 0.10max. 0.004max. 0.50 0.10 0.020 0.004 0.15 0.006 +0.10 -0.05 +0.004 -0.002 11.80 0.10 (0.465 0.004) 0~8 ?? 8.00 0.315 8.40 0.331 max. 1.20 0.047 max. 0.00 0.000 min. 0.43 0.017 0.10max. 0.004max. 0.55 (0.022) #14 #1 13.40 0.10 (0.528 0.008 ) #15 #28 0.20 (0.008) +0.10 -0.05 +0.004 -0.002
electronics km62v256c, km62u256c family cmos sram revision 04 april 1996 - 10 - 28 pin plastic small outline package (450mil ) 0 ~ 8 1.02 0.20 0.040 0.008 11.81 0.30 0.465 0.012 0.15 0.006 + 0.10 - 0.05 + 0.004 - 0.002 #28 8.38 0.20 0.330 0.008 1.27 0.050 #15 #1 #14 0.41 0.10 0.016 0.004 18.69 0.736 max 0.05 0.002 min 3.00 0.118 max 0.89 0.035 18.29 0.20 0.720 0.008 2.59 0.20 0.102 0.008 0.10 0.004 max
electronics km62v256c, km62u256c family cmos sram revision 04 april 1996 - 11 - technical information all the values in this graph are depicted by the relative value with the maximum value measured at 3.3v vcc and -40 c temperature. the basic relative value of icc2 at that condition is set into 1. all the values in this graph are depicted by the relative value with the maximum value measured at 3.0v vcc and 85 c temperature. the basic relative value of isb1 at that condition is set into 1. icc2 v.s temperature 0.500 0.600 0.700 0.800 0.900 1.000 -40 -10 0 25 40 70 85 temerature( ? ) icc2(relative value) 3.0v device 3.3v device isb1 v.s temperature 0.00 0.20 0.40 0.60 0.80 1.00 -40 -10 0 25 40 70 85 temperature( ? ) isb1(relative value) 2.7v 3.0v 1) icc2 characteristics by temperature variation 2) isb1(cmos level standby current) characteristics by temperature variation
electronics km62v256c, km62u256c family cmos sram revision 04 april 1996 - 12 - 3) idr(data retention current) characteristics by temperature variation all the values in this graph are depicted by the relative value with the maximum value measured at vdr=3.0v and 85 c temperature. the basic relative value of idr at that condition is set into 1. idr v.s temperature @ vcc=3.0v 0.00 0.20 0.40 0.60 0.80 1.00 -40 -10 0 25 40 70 85 temperature( ? ) idr(relative value)

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